Solutions for delicate challenges on the nanoscale

Diagram showing a chemical reaction process on a silicon wafer, illustrating steps involving Co3O4 and chemical compounds like TMSA and PV3, concluding with SiO2 ALD formation.

Thin film deposition processes for semiconductor manufacturing

Nanoscale charge transfer membrane

Optimized plasma pulse time of SiO₂ ALD (atomic layer deposition) process to improve the preservation yield of molecular wires (PV3) embedded in an uniform insulating SiO₂ layer (2 nm)

Schematic diagram of a fabrication process and SEM images of nanostructures. The top row shows sequential steps: AAO to AAO/N-Ctubes via CVD, hotpress on Nafion, and etching of AAO matrix. The bottom row features SEM images demonstrating a dense arrangement of nanostructures at 2 µm and 1 µm scales.

Tubular catalyst support

CVD (chemical vapor deposition) of nitrogen-containing carbon precursor on AAO (anodic aluminum oxide) and hot pressing on Nafion substrate yields vertically aligned carbon tubes upon etching of the AAO matrix

Template-based preparation of nanostructures

Diagram showing the process of creating copper nanowires through Cu electroplating on a PCTE membrane with SEM images of each stage: empty pores, copper-filled pores, and final copper nanowires.

Copper nanowires chip interconnects

Electroplating of Cu in the pores (300 nm) of PCTE (polycarbonate track etched) membrane onto a copper base substrate. The removal of the PCTE steps releases the copper nanowires.

Scanning electron micrograph of porous nanostructured material, scale bar 1 micron.

Flexible interconnected porous carbon films

Pore engineering with soft templates allows burn off of the templating agent during carbonization and simplifies conventional hard template processes