The High-Precision Light Patterning Process That Improves Each New iPhone Model

From 1 billion to 19 billion transistors in 10 years

Each new iPhone model is marketed as being faster than its predecessor. The faster processing capabilities result from advances in material science manufacturing processes that build the iPhone’s “brain”, its chip. The System-on-a-Chip (SoC) is re-designed for each generation for better performance and efficiency. Since 2010, Apple has designed its own chips in-house known as “A series” chips. (1) The main approach to improve chip performance is to increase the number of transistors. The more transistors available, the more operations per time interval a chip can perform. Transistor counts in Apple’s A-series chips climbed from 1 billion transistors in 2013 to 19 billion transistors in 2023. (2) (Image 1) The foundation for this development was laid by new nanoscale manufacturing processes that enabled higher transistor density per unit chip area. 

Image 1: Trend of the transistor count in iPhone A series chip from 2013 to 2023. Data points taken from (2).

The transistor count of Apple’s A18 Pro processor in the latest iPhone 16 (Pro) has not been disclosed yet, but it is speculated that it contains approximately 20 billion transistors or more. What is known that die size increased from 103.8 mm2 for the A17 Pro in iPhone 15 Pro to 105 mm2 for the A18 Pro in iPhone 16 Pro, providing additional space for transistors. (3) Apple’s contract manufacturer TSMC uses a second-generation 3 nm (N3E) node technology for manufacturing the A18 Pro. Compared to the A17 Pro, which is manufactured with TSMC’s first-generation 3 nm (N3B) node process, there are also improvements in the process presumed, to accommodate more transistors per area. When talking about nm node manufacturing processes, the 3 nm is not referring to an actual physical size of the transistor or a transistor component. It is a marketing term to label the manufacturing process. However, that being said there is an actual physical dimension limiting the manufacturing of chips. 

Photolithography: Patterning the small features on the chip 

This key manufacturing process is based on a technique called photolithography. (Image 2) Thereby, a pattern from a template called photomask is transferred onto a surface using light.  Initially, the substrate is uniformly covered with photoresist via spin coating. During the photolithography step, incident light causes a chemical change in the light-exposed areas. In the subsequent step, developer is used to remove either the light-exposed or unexposed surface of the photoresist. It can be differentiated between positive photoresist, which becomes soluble when exposed to light and negative photoresist, whose unexposed area is soluble in the developer. Then either deposition or etching processes are carried out on the substrate, with the remaining photoresist defining the microstructures. Finally, the photoresist is removed.

Image 2: Steps of the photolithography process to deposit nanoscale features on chips. Note: Simplified photolithography scheme (upper row right) not depicting the illumination system and projection optics.

While the mask defines the microstructure, the light is essential to transfer the fine features on the photoresist. Therefore, the resolution R is governed by the Rayleigh criterion:  R ~ NA . The resolution is determined by the wavelength of the light and the system’s numerical aperture (NA). According to the above stated formula, a higher NA leads to better resolution. Likewise, using shorter wavelengths λ improves resolution. Since UV light lies on the shorter-wavelength end of the spectrum, the development of photolithography equipment has focused on the implementing ultraviolet and extreme ultraviolet (EUV) light sources. The manufacturer of the highest-resolution EUV photolithography systems is ASML. Due to the nature of EUV light, it is more easily absorbed than other forms of light. Therefore, to minimize losses due to absorption, EUV systems are operated in vacuum and use mirrors, provided by ZEISS, instead of lenses as optical components. These specific mirrors have multilayer coatings of molybdenum and silicon (Mo/Si) for improved EUV reflectivity. As only approximately 70% of the EUV light is reflected and at least 7 mirrors are part of the optical pathway from source to wafer (4), only 10% of the light reaches the wafer.

Image 3: Development of the resolution (white) and pitch size (black) in high throughput photolithography.

Currently ASML’s TWINSCAN  NXE:3600D is the primary EUV lithography system for manufacturing 3 nm and 5 nm nodes, including the recent and current iPhone A series chips. It operates with a 13.5 nm wavelength and a numerical aperture of 0.33, enabling a resolution of 13 nm. (Image 3) While the minimum theoretical pitch size is typically twice the resolution, the actual pitch achievable in practice depends on factors such as the process conditions, photoresist materials, and mask technology.  In 2005, ASML introduced the 193 nm immersion lithography (XT:1700i), with a resolution of 45 nm. (5) The ability to create 100 nm feature pitches for the first time marked a breakthrough in semiconductor manufacturing. The future ASML TWINSCAN EXE High-NA EUV lithography is going to have a 0.55 NA and allowing for a finer intricate patterning with 8 nm resolution. (6) This corresponds to printing lines of 16 nm pitch in one single exposure, laying the foundation for the 2 nm node manufacturing.

Outlook: New transistor architecture for the 2 nm node process

TSMC is starting to open its order book this month for the 2 nm node with Apple being expected to be among the customers for contract-manufacturing the A20 chip for the iPhone 18. (7) AMD already announced this week the first high performance computing (HPC) product based on TSMC’s advanced 2 nm (N2) process technology. (8) A novelty of the 2 nm node is that it is the first generation of manufacturing nanosheet transistor technology, a type of gate-all-around (GAA) transistor architecture. (Image 4)

Image 4: Top row: Schematics of transistor architecture from historical planar to FinFET and latest Gate-All-Around (GAA) FET. Bottom row: Cross section of the gate at the channel.

This next-generation node is a significant advancement from the FinFET-based architecture employed in TSMC’s current 3 nm process. (9) The FinFET-architecture dominated the last decade, replacing the previous planar transistors, which faced issues including leakage current and short channel effects as they shrank. (10) Therefore, the FinFETs were a significant innovation to solve these issues by adding a vertical “fin” to the gate, allowing the gate to contact three sides of the channel. Since 2015 with the A9 chip, Apple has relied on the FinFET technology, which was first introduced in the iPhone 6S and iPhone 6S Plus. (11) The GAA transistors, which consist of vertically-stacked nanosheets, expands to a four-sided, all-around gate. Compared to FinFET, this gate architecture improves channel control. In addition, the current-carrying capacity of GAA transistors is increased by stacking a few nanosheets vertically, each of which is surrounded by the gate material. The 2 nm process is expected to achieve a 1.15 x increase in transistor density compared to its 3 nm predecessor, alongside with an improved performance by 15% at the same voltage and reduced power consumption by 24% to 35%. (12,13) 

Overall, the next generation of iPhones performance is going to benefit from the EUV process innovation at ASML to increase the transistor density, and an upgrade in the transistor architecture. While the material science limits with focus on the transistor count was presented in this article, there are certainly more innovations in integrated circuit design and software engineering happening simultaneously preparing your iPhone for the tool box of applications in AI.