Aligning carbon nanotubes in high density for transistors

In a previous blog post, I explored the potential for scaling the physical gate length with individual carbon nanotube field-effect transistors (CNT FETs) down to 5 nm. Leaving fundamental research behind, I will discuss in this article the current progress in integrating CNTs into next-generation integrated circuits (ICs). Unfortunately, the fabrication of ICs based on individual CNT FETs is technologically not feasible yet, as CNT FETs cannot be controllably and repeatably fabricated for the large quantities required for chips. The local environment, orientation, and chirality of each CNT would have to be exactly the same for such an idealized device to work. (1) Therefore, as an intermediate solution, horizontally aligned carbon nanotube (HA-CNT) films are envisioned as promising active channel material. The key for HA-CNT FETs is the horizontal alignment of the CNTs in an high areal density. These ideal nanotube films are predicted to enable FETs with lower power consumption, increased switching speeds, and improved electrostatic gating performance. (2) 

Image 1: Schemes of advanced fabrication techniques for horizontally aligned carbon nanotubes on wafers.

Advanced Fabrication Techniques

The recent development of fabrication techniques in solution-processed placement and aligned direct growth strategies to prepare aligned CNT arrays have brought the HA-CNT FET technology closer to practical application. Both approaches have successfully achieved the target CNT pitch of 10 nm, corresponding to a density of more than 100 CNTs per micrometre. 

Among the solution-processed techniques, a method combining purification steps with dimension-limited self-alignment (DSLA) technique has demonstrated the exceptional  semiconducting purity (>99.9999%) and high-density (125-250 CNTs/µm) criteria for large-scale wafer fabrication. (3) In this approach, a polymer selectively wraps around semiconducting CNTs, which are washed in tetrahydrofuran and re-dispersed in 1,1,2-trichloroethane through a three-step iterative process. For the DSLA procedure, the solvent 2-butene-1,4-diol is dropped onto the 1,1,2-trichloroethane solution to form a liquid film on top. The randomly orientated polymer-wrapped CNTs migrate to the interface of the two solvents and align along the wafer’s contact line as it is slowly withdrawn. However, despite achieving high alignment (within 9 degrees), HA-CNT films tested in top-gate FETs exhibit suboptimal subthreshold swing (SS) values ranging from 100 to 200 mV/decade, failing to meet the standard requirements of below 100 mV/decade for digital ICs. In addition, the HA-CNT-FETs operated in depletion mode (D-mode), meaning that they are open and conducting current between the drain and source when no gate-source voltage (VGS=0 V) is applied, making them unsuitable for low-power ICs. In contrast, in enhancement-mode (E-mode) transistors, the channel is closed by default until the application of a gate voltage creates a conductive path. To address this, subsequent research optimized HA-CNT film and gate stack, successfully fabricating E-mode HA-CNT FETs. Next to the Improved CNT alignment, a high quality HA-CNT /high dielectric constant HfO2 /metal Ti gate stack was prepared. (4) Utilizing low work function titanium instead of palladium as gate metal facilitated the realization of an E-mode p-type FET characteristics and shifted the threshold voltage (Vth) to a negative value. The resulting 200 nm gate-length (Lg) HA-CNT FETs achieved a SS of 73 mV/dec, marking significant progress toward practical application. 

Apart from the post-processing methods, direct-growth methods such as chemical vapor deposition (CVD) also had a breakthrough into high density of HA-CNT fabrication. (5) The progress was achieved by better spatial control of the catalyst nanoparticles formation and modifications in the CVD system design. The sapphire substrate was patterned into grooves to physically separate the catalyst particles preventing their sintering. Then, the catalyst for CVD was pre-seeded into the substrate by ion implantation and nucleated to form nanoparticles in situ during the CVD process on the substrate surface. A newly developed vertical spraying CVD system further optimized gas flow, enabling uniform growth of HA-CNT arrays. As a result, a one-inch wafer with a density of 140 tubes / µm could be produced. Fabricated top-gate field effect transistors with a gate length of 90 nm and channel width of 1 µm demonstrated a SS of 134 mV/decade. While this article does not explicitly state the semiconducting purity, the highest semiconducting purity of HA-CNT arrays prepared by CVD is 99.9% with a density of 11 tubes/µm. (6) 

Image 2: Semiconducting purity versus density of CNT arrays with the utility region marked by a red square and the data from (3) matching the purity and pitch targets.

Future prospects

The performance of transistors could benefit by the changing the substrate material. Glass wafers are an attractive alternative due to their high resistivity, small dielectric permittivity and low loss tangent, of which the latter two minimize the capacitance between circuits and the substrate. The DLSA method was applied to the glass wafer to arrange 230 CNTs/µm on a glass wafer, proving feasibility of the concept to prepare HA-CNT FETs on glass wafers. (7) 

While the HA-CNT films have shown tremendous progress and are the verge for applications, a randomly distributed semiconducting CNT network film was used as the channel material to build a tensor processing unit (TPU). (8) This TPU utilized CNTs with over 99.9999% semiconducting purity and build transistors with a channel length of 3 µm and a channel width of 30 µm.  The TPU contained 3,000 CNT FETs demonstrating viability of scale up. Nevertheless, authors pointed out that the performance and energy efficiency of this approach could be enhanced by using aligned semiconducting CNTs as channel materials, reducing the transistor size. 

Conclusion

The field of HA-CNT FETs has made substantial progress toward practical application, overcoming key challenges in alignment, density and semiconducting purity. Solution-processed and direct-growth fabrication methods have both contributed to these advances, enabling high-density, high-purity CNT films suitable for transistor fabrication. Nevertheless, due to the poor control on the chirality and lack of precise positioning, HA-CNT will remain in academic research lab for the foreseeable future, as industry requires scalable and reproducible manufacturing processes and reliable performing transistors.